Field of the Invention
The disclosed technology relates generally to interconnecting semiconductor chips, e.g. three-dimensional stacking of semiconductor chips and interconnecting two dimensional chips and, in particular, to testing for defects in the interconnects between the chips.
Description of the Related Technology
The semiconductor industry continues to try to integrate more functionality into a smaller form factor, increase performance, lower power and/or reduced cost. Traditionally, the industry's approaches to achieving these goals were often limited to two-dimensional approaches, including, for example, conventional scaling of CMOS, integrating multiple IP cores in a single die (System-on-Chip, SoC), integrating multiple dies in a single package (Multi-Chip Package, MCP) and integrating multiple ICs on a printed Circuit Board (PCB). More recently, the industry's approaches have included three-dimensional implementations, including, for example, integrating System-in-Package (SiP), in which multiple naked dies are vertically stacked in a single IC package and interconnected by wire-bonding to the substrate, and integrating Package-on-Package (PoP), in which multiple packaged chips are vertically stacked.
Three-dimensional (3D) stacking of chips is a hot research item, as it promises higher transistor densities and smaller footprints of electronic products. The latest evolution in this list of innovations is the so-called three-dimensional stacked IC (3D-SIC); a single package containing a vertical stack of naked dies which are interconnected by means of inter-die interconnections, optionally including through-substrate-vias (TSVs). 3D stacking based on inter-die interconnections offers the benefits of more functionality, higher bandwidth and performance at smaller sizes, alongside lower power consumption and cost; and this even in an era in which conventional feature-size scaling becomes increasingly difficult and expensive.
Currently, a lot of research and development work is done around three-dimensional stacking of integrated circuits. Two popular set-ups are illustrated in FIG. 1 (a) and FIG. 1(b). FIG. 1(a) illustrates an interposer-based 3D die stack in which multiple active dies are placed side-by-side on top of and interconnected through an interposer, such as a semiconductor, e.g. silicon, interposer. FIG. 1(b) illustrates a full 3D-SIC, in which multiple active dies are placed on top of one another.
The inter-die interconnections in such stacked ICs typically have high density, high performance, and low power dissipation. In face-to-face bonding, they are typically implemented by means of micro-bumps, e.g. Cu and CuSn micro-bumps. In face-to-back bonding, these interconnects also might contain through-substrate vias (TSVs).
Semiconductor manufacturing processes are defect-prone and hence all ICs need to be tested for manufacturing defects. Stacked ICs are no exception to this. Hence also these new inter-die connected 3D-SICs need to be tested for manufacturing defects, in order to guarantee sufficient outgoing product quality to a customer. Chip stacks should be delivered fault free as much as possible. In 3D chip stacking, the inter-die interconnections carry all interconnect signals between two dies, and hence are quite critical for functional operation of the chip. Both the inter-die interconnection manufacturing process, as well as the bonding process are delicate, and hence the inter-die interconnects are prone to defects, such as for example opens, shorts, and delay defects.
For stacked 3D-SICs, different test phases may be distinguished: (1) pre-bond test, (2) mid-post test (=testing of partial stacks), (3) post-bond test (=testing of complete stacks), and (4) final, packaged test. There are many reasons why a SIC test should be a modular test, in which the various interconnect layers, dies and perhaps embedded cores within the dies are tested as stand-alone units:
Heterogeneous stacks (combining logic, memory and analog circuitry) have different defect mechanisms, fault models, test patterns, and test pattern generation tools;
Different dies might come from different companies, who are not willing to share the implementation details of their die with others (IP protection);
The test flow involves different test phases, each with its own focus and test content. These flows are typically not fixed either, but evolve over the production life time, for example when die yields mature or yield excursions occur. Modular testing supports adaptive test flows, where tests can flexibly be included or excluded or re-ordered.
A 3D test access architecture that supports modular testing has been described in EP2372379. This architecture is based on the addition of a test wrapper around each die of the stack. The wrapper provides controllability and observability at all I/Os of the die. The wrapper supports a Serial and optionally a Parallel Test Access Mechanism (TAM) which can be flexibly configured to provide test access to one or multiple dies of the SIC simultaneously. Per die, testing the die's internal circuitry, testing the die's interconnects and a bypass mode are supported.
Common static fault models for interconnects are hard opens and shorts. They can be tested with a static (DC) test. The test access for static tests is provided by the wrappers in the 3D test access architecture described above. Dedicated test pattern generation tools are available for generating the appropriate test patterns.
However, inter-die interconnects can also exhibit delay defects, due to which the interconnect signal is transferred, but not within the specified delay margins. Testing for such delay defects can be problematic. The inter-die interconnect is very fast. Depending on the implementation (micro-bump to micro-bump, TSV to micro-bump to micro-bump, etc.) the fault-free propagation delay over the interconnect might vary from 50 ps to 500 ps (corresponding to signal transfer frequencies of 2 GHz to 20 GHz). Catching ultra-fast delay defects would involve complex timing synchronization between the two dies, whereas these dies might come from different, independent design teams (or even different companies) who do not necessarily know each other's timings. Thus, there is a need for circuitry and methods of testing for such delay defects which do not involve complex timing synchronization.